| 08:30- 09:00 |
Registration and Reception |
| 09:00- 09:05 |
Opening Ceremonies
Lung Chu, President of Asia Pacific and Corporate VP
Cadence Design Systems |
| 09:05- 09:35 |
Accelerating Design Innovation in a Complex World
Mike Fister, President and CEO
Cadence Design Systems |
| 09:35- 09:50 |
Cadence Commits to Global Research and Innovation
Ted Vucurevich, Senior VP and CTO
Andreas Kuehlmann, Fellow, Director of Cadence Research Laboratories
Cadence Design Systems |
| 09:50- 10:20 |
Characteristics of Next Generation SoC Technologies
Dr. Shaojun Wei, Professor
Tsinghua University
|
| 10:20- 10:30 |
Morning Break
(Exhibition opens) |
| 10:30- 12:00 |
Panel - Olympic Beijing 2008 Inspires Chinese Electronics Innovation
Panelists including Executives from China IC Ecosystem
|
| 12:00- 13:00 |
Lunch
(Demo booths open at 12:30-13:00) |
| |
Track I
Front-end Closure |
Track II
Advanced Node Design
|
Track III
Custom IC Design
|
Track IV
IC Packaging and PCB Design
|
13:00- 13:30
|
Metric Driven Verification for Full Chip SoC Verification
Apurva Kalia, R&D Vice President, Advanced Verification, Cadence |
Encounter to Address Power, Manufacturability and mixed signal challenges for high-end digital consumer, computing and networking applications
Frank Leu, VP of Engineering, IC Digital, Cadence |
Leveraging Cadence Simulation Technology and Environments for Mixed-Signal Verification
Zhihong Liu, Corporate VP, Simulation, Cadence |
13:00-13:40
Allegro PCB and IC Packaging Roadmaps
AJ Incorvaia, VP R&D, Cadence |
13:30- 13:50
|
Utilize early chip planning strategies to reduce IC size, power and cost
Adam Traidman, Group Marketing Director, Cadence |
IC Design Trend in the Next Decade
Arthur Ting, Director, Design Consulting & Service, SMIC Beijing |
Low Power AMS/RF SOC design methodology for 65/45nm
Bob Pau, Sr. Staff Application Engineer, Cadence |
13:40-14:00
Applying APD and APSI to perform Silicon-Package-Board Co-design
Coolsand
14:00-14:30
Increasing the System Performance and Form Factor in RF SiP Design
Charlie Shih, Principal AE, Cadence |
13:50- 14:10
|
Tuning RTL Compiler to optimize power and performance in large, high-speed SoC designs
David Weir, Lead Design Engineer, Cadence |
The success of Faraday power gating design solution
Faraday |
14:10- 14:30
|
Practical Aspects of Nanometer Testing for Nanometer Chips with Encounter Test Tool Suite: A Perfect Solution
Anis Uzzaman, Product Marketing, Cadence |
CTA: A New Clock Tree Analysis Tool in Encounter->Debug Complex Clock Tree for Multigigahertz Chip Design with New Encounter Clock Tree Analyst
Terri Yu, Sr Member of Technical Staff, Cadence |
Substrate noise simulation of DC-DC converter using Cadence QRC
Freescale |
14:30- 14:50
|
Palladium enables H.264 Encoder design
Fullhan |
Chip-Package Static Power Analysis with VoltageStorm & APSI
Coolsand |
Cadence PAS accelerates Mixed Signal/RF PDK development
GSMC |
SiP Application in CMMB TV Tuner Module
Ambit |
14:50- 15:10
|
an Advanced Low Power Design Experience with CPF to Accelerate Power Closure
Global Unichip |
Low Power Back End Design Introduction
Alex Zheng, Lead PV Engineer, Cadence |
A 90nm Analog IC Design enabled by Cadence Paratistic Extraction and Post-Layout Simulation Technologies
Datang Microelectronics |
New Field Solver Technologies in Allegro High Speed Simulation
Paul Musto, Group Director R&D, Cadence |
| 15:10- 15:40 |
Afternoon Break
(Demo booths open) |
15:40- 16:00
|
CPF eases advanced Low-Power Verification
VIA |
A Structured Design Service Model for Customer's Project Success
Chen Cheng, Lead Services AE, Cadence |
Virtuoso Passive Component Designer of Spectre RF
Bin Lu, Member of Technical Staff, Cadence |
15:40-15:55
A New EBD model based Methodology to Analyze the SI effect between DDR2 Module and FPGA platform
VeriSilicon
15:55-16:10
Leveraging Allegro System Architect for integrating FPGAs
Jian-wei Hu, Lead AE, Allegro Platform, Cadence
16:10-16:30
Improving RF PCB Design Productivity
Dingru Xiao, Staff Product Engineer, Cadence
16:30-17:00
Engineering Implementation of High Performance PCB Design
EDADOC
|
16:00- 16:20
|
Simplified Silicon Virtual Prototype (SVP) Flow: A Solution for Fast Chip Estimation in Large Chip Design
Zhao Jin, Lead PV Engineer, Cadence |
Using Silicon Diagnostics to Improve Manufacturability
Tom Jackson, Product Marketing Director; Anis Uzzaman, Business Development Manager, Cadence |
Improve your design using spectre MDL
Hong Zhou, Sr. PV Engineer, Cadence |
16:20- 16:40
|
Implement a Class based Highly Effective Verification Environment using Open Verification Methodology (OVM)
China Academy of Space Technology |
Timing Aware MasterPlan to shorten your project period
Candy Wei, PV Engineer, Cadence |
Design of LC-VCO with VPCM in Deep Sub-Micron RF CMOS
SMIC |
16:40- 17:00
|
Static Timing Estimation and Analysis at Nanometer Process Node
Institute of Computing Technology of Chinese Academy of Sciences |
Design and Analysis of Mesh-Local-Tree Clock Architecture in Encounter
Grace Gu, PV Engineer, Cadence |
A Low-voltage Fully-integrated CMOS Frequency Synthesizer for 3.5-GHz Applications
SMIC |
| 17:00- 17:30 |
Wrap up and closing
|
